Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation (Systems on Silicon)
Scott Hauck, André DeHon
Format: PDF / Kindle (mobi) / ePub
The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
. Views of FPGA programming beyond Verilog/VHDL
. Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways
block CB Switch box CB CB Logic block Switch box CB Logic connect lines FIGURE 1.8 ■ Local (direct) connections and L2 connections augmenting a switched interconnect. 232 (16) 131 (4) 434 (32) FIGURE 1.9 ■ Hierarchical routing used by long wires to connect clusters of logic blocks. Within this block, local, nearest-neighbor routing is all that is available. In turn, a 2 × 2 cluster of these clusters is formed that encompasses 16 logic blocks. At this level of hierarchy, longer wires
addresses) may change the program behavior; it becomes acute in concurrent systems. If there is variability in the relative 96 Chapter 5 ■ Compute Models and System Architectures timing of operations, the order of events can change, and without care this may result in different visible application behavior. Further, as we scale to different hardware capacities, we may exploit different amounts of concurrency and deliberately change the order of primitive events. Nonetheless, we might want
while others are busy. Cyclic dependencies in the dataﬂow graph may make it impossible to keep all the operators active simultaneously. To use the datapath hardware efﬁciently in cases such as these, it is often useful to share a physical datapath among multiple operators. In the simplest case, we share identical operators so that the datapath remains the same, only adding the unique state associated with each of the operators. In more complicated cases, we might generalize the datapath so that
output channels. Message passing When we connect processors or FSMs with communication channels, we often ﬁnd it inefﬁcient to commit dedicated, point-to-point links. ■ ■ ■ The data rate on point-to-point channels between processors, operators, or FSMDs can often be too low to merit a dedicated channel. Dedicating point-to-point channels between processors, operators, or FSMDs can be too expensive for an implementation. Individual units of control may only need to communicate infrequently.
generate hardware as a function of some changeable parameter. This is a useful technique for code reuse when we need several variants of an element in the same design (e.g., an 8-bit and 16-bit adder in the same design). Certain design parameters are often not known until late in the design cycle, and some can change as the design speciﬁcation evolves to meet customer requirements. It might also be necessary to perform a parametric design space exploration based on certain variables before