This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.
is the same in each case, sB may have different shapes, a temporal relationship (or causality relationship) between sA and sB exists in the sense that sA ‘causes’ sB , thereby preceding the switching event by an amount of time required for the physical switching process to propagate through the circuit structure, 2.2 Synchronous VLSI Systems • 11 regardless of shape, sB has the same logical meaning, that is, that the state of the circuit at point B changes from low to high; this low-to-high
additional indices n and p are used to indicate which type of transistor is being considered, N-channel or P-channel, respectively. To first order, the drain current Idsn through a long-channel NMOS transistor4 can be modeled by the classical Shichman-Hodges set of equations [22]: ⎧ 1 2 ⎪ ⎪ , Vgsn ≥ Vtn and Vgdn ≥ Vtn ⎪βn (Vgsn − Vtn )Vdsn − Vdsn ⎪ ⎪ 2 ⎪ ⎪ ⎪ ⎪ (triode or linear region) ⎪ ⎪ ⎨ 1 2 Vgsn ≥ Vtn and Vgdn ≤ Vtn Idsn = βn (Vgsn − Vtn ) , 2 ⎪ ⎪ ⎪ (pentode or saturation region) ⎪ ⎪ ⎪ ⎪ ⎪ 0,
the Fi output of Ri , i.e., the sum di = ticd + kTCP − ΔF L + DCQm of the earliest arrival time of the leading edge of Ci and the minimum clock-to-Q delay of Ri , 2. The minimum propagation delay DPi,fm of the signals through the combinational logic block Lif and interconnect wires along the path Ri ❀Rf . 60 4 Timing Properties of Synchronous Systems Therefore, af can be described as i,f Fi af = di + DPi,fm = ticd + kTCP − ΔF L + DCQm + DP m . (4.10) By substituting (4.10) into (4.9), the
this section are built on the timing relationships among the signals of a latch similar to those used in Sections 4.7 and 4.8. Specifically, it is guaranteed that every data signal arrives at the data input of a latch no later than δSL time before the trailing clock edge. Also, this data L time after the trailing edge, i.e., no signal must remain stable at least δH L time after the latch has become new data signal should arrive at a latch δH opaque. 4.9.1 Preventing the Late Arrival of the Data
caused by other factors are dominant, improvement through delay insertion is not possible. In experimentation, such circuits are reported to be one of the two cases where the delay insertion method is inapplicable (e.g., delay insertion method is not beneficial). Let the source and sink registers in a reconvergent path system be called the divergent register Rd and the convergent register Rc , respectively. Let pd{i1 ...in }c define a reconvergent path starting from register Rd , continuing through
